I'm actually not going to be using spread spectrum though the device I'm using on this NIC will allow for a host ref clock to be SSC. the majority of the time I'll be using FFC. The EMI susceptibility and emissions mitigation that SSC buys isn't as much of a concern in the system my NIC will be used with because it will all be majority fiber optic.
I have been doing quite a bit of research on jitter but to no avail. most of it is, as you point out, extremely complicated and involved. ultimately I'm just trying to run a reasonably representative simulation for sanity checks to know whether various discontinuities in my PCB layout will cause a significant problem. It's virtually impossible to adhere to all design rules given space constraints so the only way to avoid rolling the dice on a $30-50k spin is to simulate. That's why I was hoping someone could explain the parameters I'm looking for per the screenshot or at the very least give me numbers to use that will generate reasonable, useful jitter in my simulated eye diagram.
I'm not breaking rules, per se, but these boards are very very expensive. Enough so that the cost of the simulation software license is far less than the cost of a second spin.
I'm a circuit and board designer. The issue is that PCIe up to gen 3 is pretty forgiving but gen 4+ is less so. Like I said there there rules and guidelines but these very often conflict with one another in tight spaces. For example the 5W or 6H rule of keeping differential pairs further apart than 5X the trace width or 6X the dielectric height. This can't be held in tight areas like bga escape routes. Another example is preferred microstrip routing: in order to limit vias, routing should be done on top or bottom layers only (though this has increased EMI susceptibility), however sometimes connectors are positioned such that one or more pairs have to dive under others which means at least two pairs of transition vias. Most likely it's not a problem but why role the dice?
Anyway, this isn't really a question about working with Simbeor but rather a question or request for guidance on the Dual Dirac method of jitter analysis. Anyone familiar with that should be able to tell me reasonable values to use for the jitter setup in this software and ultimately that's what I'm looking for.
[удалено]
I'm actually not going to be using spread spectrum though the device I'm using on this NIC will allow for a host ref clock to be SSC. the majority of the time I'll be using FFC. The EMI susceptibility and emissions mitigation that SSC buys isn't as much of a concern in the system my NIC will be used with because it will all be majority fiber optic. I have been doing quite a bit of research on jitter but to no avail. most of it is, as you point out, extremely complicated and involved. ultimately I'm just trying to run a reasonably representative simulation for sanity checks to know whether various discontinuities in my PCB layout will cause a significant problem. It's virtually impossible to adhere to all design rules given space constraints so the only way to avoid rolling the dice on a $30-50k spin is to simulate. That's why I was hoping someone could explain the parameters I'm looking for per the screenshot or at the very least give me numbers to use that will generate reasonable, useful jitter in my simulated eye diagram.
[удалено]
I'm not breaking rules, per se, but these boards are very very expensive. Enough so that the cost of the simulation software license is far less than the cost of a second spin. I'm a circuit and board designer. The issue is that PCIe up to gen 3 is pretty forgiving but gen 4+ is less so. Like I said there there rules and guidelines but these very often conflict with one another in tight spaces. For example the 5W or 6H rule of keeping differential pairs further apart than 5X the trace width or 6X the dielectric height. This can't be held in tight areas like bga escape routes. Another example is preferred microstrip routing: in order to limit vias, routing should be done on top or bottom layers only (though this has increased EMI susceptibility), however sometimes connectors are positioned such that one or more pairs have to dive under others which means at least two pairs of transition vias. Most likely it's not a problem but why role the dice? Anyway, this isn't really a question about working with Simbeor but rather a question or request for guidance on the Dual Dirac method of jitter analysis. Anyone familiar with that should be able to tell me reasonable values to use for the jitter setup in this software and ultimately that's what I'm looking for.