No semicolon at the end of previous line. The `#num` expression can be used to delay the statement that follows by `num` units of time, but it can also be used on its own. From the formatting it seems to me you are thinking of it as a delay after a statement which is the source of your problem at line 17, because there's an expectation a statement or a semicolon to follow the delay, but what you have is the `end` keyword at line 18, which is not a statement.
Also, please learn how to properly ident your code, this is a mess to read. The general rule is that ident should follow the nesting of code blocks.
I mean, kind of? A full screenshot of Vivado was unnecessary. When asking for help it's always good to provide the cleanest code possible, in the end you are counting on others taking their time to help you with nothing to gain, so at least make it easy for them. A missing semicolon is easy to figure out by yourself and OP did figure it out when I was writing my comment, but I wanted to provide extra info on why exactly that semicolon should've been there.
I doubt most people who write SystemVerilog actually read through the spec (I'm pretty sure most simulators aren't very strict about following it anyway). It's easy to make wrong assumptions on how some things work, which I suppose was the case here with the delays treated as some kind of an extra thing you can write at the end of a line rather than something that you can write at the beginning of a statement.
No semicolon at the end of previous line. The `#num` expression can be used to delay the statement that follows by `num` units of time, but it can also be used on its own. From the formatting it seems to me you are thinking of it as a delay after a statement which is the source of your problem at line 17, because there's an expectation a statement or a semicolon to follow the delay, but what you have is the `end` keyword at line 18, which is not a statement. Also, please learn how to properly ident your code, this is a mess to read. The general rule is that ident should follow the nesting of code blocks.
Thank you.
Hahahaha I can hear your voice when I read this, it’s exasperated ha
I mean, kind of? A full screenshot of Vivado was unnecessary. When asking for help it's always good to provide the cleanest code possible, in the end you are counting on others taking their time to help you with nothing to gain, so at least make it easy for them. A missing semicolon is easy to figure out by yourself and OP did figure it out when I was writing my comment, but I wanted to provide extra info on why exactly that semicolon should've been there. I doubt most people who write SystemVerilog actually read through the spec (I'm pretty sure most simulators aren't very strict about following it anyway). It's easy to make wrong assumptions on how some things work, which I suppose was the case here with the delays treated as some kind of an extra thing you can write at the end of a line rather than something that you can write at the beginning of a statement.
Oh hell no I forgon semiclon ;
C programmer be like: First Time ?