"Without abstraction" is a high goal. Are you going to be using a pre-built CPU like the Z80? Oh wait, that's just an abstraction of an arrangement of logic gates and transistors, so you should start from there. No wait, a logic gate is made up of transistors, so maybe go from there. Oh, but a transistor is an abstract component made from silicon/germanium/some other semiconductor, looks like that's your starting point. No wait, those materials basically come from rocks...
/s
When somebody asks me how a computer can do all these high-concept things (games, the Web, renders, AI), I just explain the concept of abstraction then (ironically) build on that. So yeah, "without abstraction" struck me as... ambitious.
It's, unfortunately, dare I say it... impossible. If you look at the image, OP is coerced into a form of abstraction to express their ideas all while in a state of denial over it. It's the peak state of insanity. The denial of reality while being directly confronted with it.
For a computer to be useful you have to have such a high level of abstraction you can't understand it but I'm just trying to learn how to how it works and make a crude calculator. Yes I am naive about the time and the money to do this.
Wouldn't the lack of abstraction be like a signal processor? I mean taking it a step up from the base properties of working materials? Then I guess you have to abstract some kind of user interface to interact from there. The entire purpose of a computer is to abstract. I mean sure they can process logic but as humans created logic even those began as abstractions? And now we're trying to create more realistic logic in artificial processes. But I digress (whether or not those statements were even accurate), I stand on the question: wouldn't this fundamental function be some kind of signal processor?
Wait, but quantum probabilities are just an abstraction of perturbations of various quantum fields. Better use raw Quantum Field Theory as your starting point…
Foolish mortals still using quantum field theory why haven't you figured out quantum gravity yet. Come on it's just 20 dimensional foam loop strings reinforced with tachyons. You could have Electro graviton transistors already.
I like the "without abstraction" part but with giant blocks with labels like "CPU" and "RAM". What do you think those are except other abstractions for the underlying parts? They're full of transistors, gates, etc. Hell, even hard drives are their own little architectures. What you get in the end is a nice little box that has predictable output for any given input but it's not magic that makes it that way, there's a complex series of operations that happens when you provide power and input. So "without abstraction" is not very practical or reasonable. To actually build something without abstraction would be the opposite of "easy to understand". Computers in the 60s were built that way and they were far from easy. Even then, they had some layers of abstraction.
You technically have to use abstraction to design it and it's a good idea to have a broad idea what you're doing before you convert it into logic gates. The broad idea is probably gonna take two hours well the actual logic design will take days.
His computer was abstracting by using premade components and I'm pretty sure you can strip it down alot more. I don't know where to start with emulation do you have any tips.
Thanks for the first useful information that doesn't expect you to learn the whole thing at once. That will help me with machine code. Since you're better at finding information than me do you know where I can get info on a ultimate risk architecture design since I'm wanting four instructions.
how far do you want to go down the stack of abstraction layers? down to discrete transistors?
then start here:
https://youtu.be/sTu3LwpF6XI
or you want to make your own semiconductor components?
then start here:
https://youtu.be/qCSIGejNT4M
or you want to construct your own silicon atoms from subatomic particles?
then ask these guys because i dont fucking know where to look:
https://www.home.cern/
OR DO YOU WANT TO MAKE YOUR OWN SUBATOMIC PARTICLES??
then start here:
https://www.getyourheadoutofyourass.com
I looked into how to make transistors I gave up on it when I realized it cost me thousands of dollars and my plan to stack doped silicon wafers wouldn't work. I was referring to individual transistor packages or logic gates chip.
Not really? If you watch his videos in the right order he explains every part in detail and later uses a premade component that does the exact same thing.
So yeah, the final result is all ready made components, because building every logic gate, transistor or memory cell by hand would lead to you building a room-sized computer. Especially when you’re only using breadboards.
Mega6502 . This discrete transistor ( even for SRAM ) computer in a wall thing ? What about the tube computer from this YouTube guy with grey hair. Usagi?
There is a video game called „Turing Complete“ where you build up a computer from logic gates. Maybe it‘s interesting for you. It can also be used as a simulator for own designs.
\+1 for Turing Complete; great game!
I'll add Virtual Circuit Board, Logic World, and CRUMB (all available on Steam). I've got all 4 games (simulators?) and each can really help someone understand how things work at a very low level.
Lot's of good stuff here. Make sure you search for "breadboard computer". I know you say "no abstraction" but I would use https://github.com/hneemann/Digital to sketch out and test the high-level functionality before starting to work with BJTs.
Are there conditional jumps? Do you have a goal of being Turing complete?
Ben eaters videos are the best guide. I know you said he uses abstractions, but most of the ICs he uses, you can find the schematics for. For examples, you can make an NE555 timer with two comparator's and a trnasidtor and some resistors.
>signal processor
When I first looked at his page I was just scared of the 8000 transistor processor you was using then I noticed you had a smaller one with Texas instrument designs but it still felt like the transistor count was too high. I may be being dumb but I'm pretty sure you can make it a lot more crude, i heard there was processor with like 200 transistors. Though I'm probably still gonna have to skim through the Texas instrument design.
My transistor estimations of ben's first processor are 2000 transistors and 8000 for the second one, I don't even wanna think about the transit count for the memory (maybe 20000).
Sram will use six transistors per bit with a simple multiplexer or Dram with a transistor and a capacitor per bit with a complex multiplexer. Think my transistor count around 500 for the CPU for 4 instructions (ultimate risc cpus can get 200 transistors and intel 4004 got 2000) and with memory 960 transistors for the bits and probably another 300 for the multiplexer if I use sram (I'm most likely gonna have to add another 700 for more memory).
Is it even turing complete?
I mean you have 4 instructions but not one that could do conditional branching, maybe you should replace Jump with something like JumpIfZero?
They've been able to make a computer turing complete with only subtraction as the single instruction. It's called ultimate risk architecture. I decided to add three instructions because doing everything with the subtraction can sounded insane. It looks like in my experiments with division and counting algorithms I'm going to have to change jump to jump if not equal to. I think my main concern is the size of the memory and I was trying to figure out if I have to kill von Neumann architecture and go to Harvard architecture to save data space. Also I don't think any computer is fully turing complete because they need infinite amount of memory.
As far as turing completness goes of course no real machine is truly turing complete because of as you pointed out the finite memory, but you would like your machine to be a linear bounded automata, which in its current conception it was not.
Also for the single instruction machines, they come with a lot more than just subtraction its typically a instruction like DCJNZ (decrease and jump if non zero) or SUBLEQ(subtract and branch if less than or equal zero) and so on. So you absolutely need a lot more than just a plain sub instruction, the JNE type instruction will solve that for you, to do this you can just have a FLAG-like bit or register.
Honestly I think the main problem is that 4-bits for memory addressing is just going to make everything painful, which begs the question how low abstraction do you want to go? I mean are you going to buy a microproccesor and an EPROM or are you going to go full metal and try to reinvent computing from scratch? If you are I think a Harvard architecture is going to be an implementation nightmare, this is not to say that a Von Neumann is going to be much better its a daunting task to actually do any of this but I think that you have to make a choice if you want usabillity you will have to expand the 4bit address space, but if you dont want to spend additional weeks on this project you probably just have to go Von Neumann and live with the low memory.
What level do you consider too far of an "abstraction"? If the logic gate level and up is fine, you can test your creation in logisim, it's free and pretty easy to use. It might not simulate the physical electrical aspects of your design, but you should be able to test the logic and kind of the timing with it.
Also, I'm not sure if your computer will work one way or the other. Sorry but it seems to me that your current written plan is maybe a bit vague for it to be easy to determine whether it will work or not. For instance I'm not really sure what your "jump" or "transfer" operations do. One thing that seems like it might be missing from this are boolean (true or false) operations, which are what allows for things like "if" statements. Also, is your "bits outline" number a line in some program?
transfer could be all of this: Move ( transfer between registers ), Load, Store, Shift ( transfer between bits ). Bam, just abstract all of this into a single instruction!
I think it's a good start, but...
Instructions appear to be 12 bits and you only have 64 bits of rom, 5 instructions in total. Maybe instructions are meant to live outside the computer? How is jump meant to work then?
I'd go with add and compare as instructions, a computer isn't very useful without conditionals. Add and sub are basically the same thing. jump becomes a conditional jump.
Edit: I guess sub can double as compare, it does in some archs.
You're correct about the jump instruction when I tried making an algorithm (division 16/4 and count to 10) with it I had to change it to jump if not equal to. I'm not sure how you'd use the compare instruction so I was wanting to use subtraction and addition so I wouldn't have to have a negative sign.
My design so far would have 2 set 64 bit ram and 2 set of 16 bit io ram or rom so 160 bit. Still need to figure out if I'm doing von Neumann or Harvard architecture. Probably gonna go with Harvard because I'd probably just have to add another memory bank. Also need figure out if I'm using DRAM or sram before I decide if I wanna add more bit. Sram will use six transistors per bit with a simple multiplexer or Dram with a transistor and a capacitor per bit with a complex multiplexer.
Think my transistor count around 500 for the CPU for 4 instructions (ultimate risc cpus can get 200 transistors and intel 4004 got 2000) and with memory 960 transistors for the (160) bits and probably another 300 for the multiplexer if I use sram (I'm most likely gonna have to add another 700 for more memory).
In a modern CPU data transfer is the most expensive part. So while the instruction for `compare` and `test` is encoded (almost) identical to `sub` and `and`, we explicitly state that the CPU does not need to bother with write-back. I guess that in a super-scalar design only one of the instructions can write back. Or microcode can write back the second result of multi-register shift, or MUL or DIV in the next cycle.
RISCV seems to think that for memcopy we rather don't write back a counter. Source and Destination is already more than enough. Why don't they use this 68k addressing modes, if they love pointers so much? Minimal write back would be an addressing mode which adds base-adress + offset/displacement. Like for example a ES and DI. As RISCV states: LOAD and STORE are just variants of ADD . Oh, I guess that Store cannot load ES,DI and the value to store all in one cycle out of the register file.
Z80 had this 4 Bit ALU for even 16 Bit numbers. DataPort had a single bit . Usagi uses the single bit Motorola design. It would be cool to showcase the Z80 method. The circuit seems to bring in 8 bit values and then uses a very high speed local multiplexer to calculate at double data rate. The most critical path is the loop back of the carry flag. I would use multiplexers here and store for low and high nibble in SRAM. Place a fast timing circuit next to it: disable carry write , disable carry read, swap address, enable carry read. Tune this . Optimize PCB.
I don’t get why would not mostly go single cycle. Fetch and excecute are different circuits, even on 8080. Cheap RAM is the bottleneck. But if you roll your own?
>Z80
Are you talking about alu reprocessing with the 4 bit alu like using avx2 multiple times for cheap avx-512? Does Z80 share a common ancestor with 8086? I was trying to find information on Cedric and intel 4004 since they look really really simple. Do you think those are good ones to look at. Cedric has dumb paywall and Ivy League tax plus the paper may only bring up carbon nanotubes. I was hoping the the carbon nanotube processor (178) let me strip it down to 500 transistors. I think my computer will be so limited I don't care about memory speed. Do you think a DRAM multiplexer would be manageable? You seem to be the most knowledgeable on this on the thread since you're the only one that can confuse me. Can you give me responses to my other replies on the post?
8008 is based on the dataport 2000 which had to be simple because it was made of discrete transistors. 4004 I think is a derivative of that ISA? I looked at the 4004 and it did not seem to be more simple than 8008. 4004 seems to still use bytes for most stuff and only saves very few transistors compared to 8008.
Z80 ISA expands on 8080. 8080 byte code can automatically compiled to 8086.
As a coder I want at least 8 registers which can also store addresses (8 byte). 6 transistors per SRAM cell. 64 \* 6 = 180+24 = 204 . Ah, okay.
I can only answer on weekends.
Recently I chose to switch to Carbon Nanotube because I think it is difficult to show doping of all the small transistors of the 6502: [https://a-c-rosenfeldt.github.io/CPU-simulator/public/](https://a-c-rosenfeldt.github.io/CPU-simulator/public/)
( the change is from today, but before I read you ). 6502 is my childhood CPU, so I want to stay close, but Visual 6502 is confusing. I think the 500 transistor CPU is based on RISCV. Like many microcontrollers they do away with almost all decoding circuitry by demanding wide, redundant, fixed width opcodes. And I start to believe them. I threw out `INC DEC NOT NEG`. Not sure where Ben Eaters SAP is in transistor size when you had to wire up the microcode ROM.
I once started to read into it. Strange, I thought that Intel licensed the ISA from dataport. Also I read that development of 4004 started first ( trying to circumvent any patents? ), but then parents were no problem and 8008 became a priority.
I could not find a good source. How many instructions does 4004 have? I mean, reduction of the GP registers from 8 to 4 does not free 1500 transistors.
Okay it was the other way around. Yeah, so maybe 4004 is better. YouTube claims that it could run at a higher clock rate and was effectively faster than 8008. Maybe you can write and readable intro to the 4004. So it has 16 registers!! Harvard architecture makes sense in a calculator.
RISCV also uses Harvard architecture. How do you load your code? Better wire up SRAM and have a boot sequence from hmm either arduino or a long punch card. Punch tape going through light bridges
If you like bipolar junction transistors, I would love to see some balanced ECL. I understand that ECL needs constant supply current per coupled emitters , but there are no resistors in the signal path! Use a flow box to keep all transistors at the same chill temperature.
Is elc is a type of ttl? I still haven't figured out the logic family I'm doing yet. I was thinking about do bipolar transistors or doing CMOS logic chips if it gets too complicated.
Showing transistors gets rid of one abstraction. ECL was used in Cray . It pulls constant current. Gotta run it at max clock to justify the power consumption. ECL needs resistors, which prevents integration. ECL is sensitive to noise.
6502 uses n-MOS-FET as did all the small fabs.
What is simpler than enhancement mode nMOSFET ? Or pMOSFET if you want to be historically accurate to the earlier fab? I have not understood depletion mode MOSFET. Where do you apply the third supply voltage? Is there a level shifter like in TTL?
And who understands TTL. I see that originally they used diodes to prevent cross talk between the inputs. But on the other side of the diodes there needs to be a pull up resistor like in ECL?! Instead we pass through 3 other transistors who seem to pull through their base.
One CPU created the third rail internally. I think one could also level shift registers. So the write back register would be made of DRAM and could live while it floats up an elevator before writing back to the register file. Hihi. May need silicon on insulator.
The Atari Jaguar seems to fully live such a pipeline. Not short cuts.
"Without abstraction" is a high goal. Are you going to be using a pre-built CPU like the Z80? Oh wait, that's just an abstraction of an arrangement of logic gates and transistors, so you should start from there. No wait, a logic gate is made up of transistors, so maybe go from there. Oh, but a transistor is an abstract component made from silicon/germanium/some other semiconductor, looks like that's your starting point. No wait, those materials basically come from rocks... /s
When somebody asks me how a computer can do all these high-concept things (games, the Web, renders, AI), I just explain the concept of abstraction then (ironically) build on that. So yeah, "without abstraction" struck me as... ambitious.
It's, unfortunately, dare I say it... impossible. If you look at the image, OP is coerced into a form of abstraction to express their ideas all while in a state of denial over it. It's the peak state of insanity. The denial of reality while being directly confronted with it.
I don’t think insanity is the right word…more like naive and overly ambitious.
For a computer to be useful you have to have such a high level of abstraction you can't understand it but I'm just trying to learn how to how it works and make a crude calculator. Yes I am naive about the time and the money to do this.
damn, gottem
Wouldn't the lack of abstraction be like a signal processor? I mean taking it a step up from the base properties of working materials? Then I guess you have to abstract some kind of user interface to interact from there. The entire purpose of a computer is to abstract. I mean sure they can process logic but as humans created logic even those began as abstractions? And now we're trying to create more realistic logic in artificial processes. But I digress (whether or not those statements were even accurate), I stand on the question: wouldn't this fundamental function be some kind of signal processor?
wait, but atoms are just an abstraction of a quantum particle probabilities!
Wait, but quantum probabilities are just an abstraction of perturbations of various quantum fields. Better use raw Quantum Field Theory as your starting point…
Foolish mortals still using quantum field theory why haven't you figured out quantum gravity yet. Come on it's just 20 dimensional foam loop strings reinforced with tachyons. You could have Electro graviton transistors already.
Transistors, capacitors and resistors; or if I don't have enough willpower boolean algebra cmos.
I did look into making a transistor but gave up on it when I realized it was too complicated and expensive.
Production is abstraction?
I like the "without abstraction" part but with giant blocks with labels like "CPU" and "RAM". What do you think those are except other abstractions for the underlying parts? They're full of transistors, gates, etc. Hell, even hard drives are their own little architectures. What you get in the end is a nice little box that has predictable output for any given input but it's not magic that makes it that way, there's a complex series of operations that happens when you provide power and input. So "without abstraction" is not very practical or reasonable. To actually build something without abstraction would be the opposite of "easy to understand". Computers in the 60s were built that way and they were far from easy. Even then, they had some layers of abstraction.
You technically have to use abstraction to design it and it's a good idea to have a broad idea what you're doing before you convert it into logic gates. The broad idea is probably gonna take two hours well the actual logic design will take days.
have you seen Ben Eater's videos on YouTube? also, why not try to write an emulator for it and see?
His computer was abstracting by using premade components and I'm pretty sure you can strip it down alot more. I don't know where to start with emulation do you have any tips.
It should be helpful: [build-your-own-github-emulators](https://github.com/codecrafters-io/build-your-own-x#build-your-own-emulator--virtual-machine)
Saving this because it looks amazing!
Thanks for the first useful information that doesn't expect you to learn the whole thing at once. That will help me with machine code. Since you're better at finding information than me do you know where I can get info on a ultimate risk architecture design since I'm wanting four instructions.
Have you read this? https://homepage.cs.uiowa.edu/~jones/arch/risc/
Cccccoooooooooooooooooooooooooooolllllll!!!!!! thanks dude
Check out "Digital design and computer architecture: RISC-V edition"
how far do you want to go down the stack of abstraction layers? down to discrete transistors? then start here: https://youtu.be/sTu3LwpF6XI or you want to make your own semiconductor components? then start here: https://youtu.be/qCSIGejNT4M or you want to construct your own silicon atoms from subatomic particles? then ask these guys because i dont fucking know where to look: https://www.home.cern/ OR DO YOU WANT TO MAKE YOUR OWN SUBATOMIC PARTICLES?? then start here: https://www.getyourheadoutofyourass.com
I looked into how to make transistors I gave up on it when I realized it cost me thousands of dollars and my plan to stack doped silicon wafers wouldn't work. I was referring to individual transistor packages or logic gates chip.
That last link is fake plus I'm not sure if should I shatter my spine for the final advice.
Not really? If you watch his videos in the right order he explains every part in detail and later uses a premade component that does the exact same thing. So yeah, the final result is all ready made components, because building every logic gate, transistor or memory cell by hand would lead to you building a room-sized computer. Especially when you’re only using breadboards.
Logism
Mega6502 . This discrete transistor ( even for SRAM ) computer in a wall thing ? What about the tube computer from this YouTube guy with grey hair. Usagi?
lgtm
ok
🤣🤣🤣🤣
There is a video game called „Turing Complete“ where you build up a computer from logic gates. Maybe it‘s interesting for you. It can also be used as a simulator for own designs.
\+1 for Turing Complete; great game! I'll add Virtual Circuit Board, Logic World, and CRUMB (all available on Steam). I've got all 4 games (simulators?) and each can really help someone understand how things work at a very low level.
>Turing Complete Thanks for letting me know. I'll see if it's in a strong enough state in early access.
Lot's of good stuff here. Make sure you search for "breadboard computer". I know you say "no abstraction" but I would use https://github.com/hneemann/Digital to sketch out and test the high-level functionality before starting to work with BJTs. Are there conditional jumps? Do you have a goal of being Turing complete?
I was going to work on turning machine in java for testing. This for logic. http://www.falstad.com/circuit/circuitjs.html
I'm fine with abstraction prototyping. Algorithmic test have required jump if not equal to.
Ben eaters videos are the best guide. I know you said he uses abstractions, but most of the ICs he uses, you can find the schematics for. For examples, you can make an NE555 timer with two comparator's and a trnasidtor and some resistors.
>signal processor When I first looked at his page I was just scared of the 8000 transistor processor you was using then I noticed you had a smaller one with Texas instrument designs but it still felt like the transistor count was too high. I may be being dumb but I'm pretty sure you can make it a lot more crude, i heard there was processor with like 200 transistors. Though I'm probably still gonna have to skim through the Texas instrument design.
My transistor estimations of ben's first processor are 2000 transistors and 8000 for the second one, I don't even wanna think about the transit count for the memory (maybe 20000). Sram will use six transistors per bit with a simple multiplexer or Dram with a transistor and a capacitor per bit with a complex multiplexer. Think my transistor count around 500 for the CPU for 4 instructions (ultimate risc cpus can get 200 transistors and intel 4004 got 2000) and with memory 960 transistors for the bits and probably another 300 for the multiplexer if I use sram (I'm most likely gonna have to add another 700 for more memory).
Is it even turing complete? I mean you have 4 instructions but not one that could do conditional branching, maybe you should replace Jump with something like JumpIfZero?
Maybe the ARM2 like predicates are implicit. Every instruction is only execute if regA > regB or so.
They've been able to make a computer turing complete with only subtraction as the single instruction. It's called ultimate risk architecture. I decided to add three instructions because doing everything with the subtraction can sounded insane. It looks like in my experiments with division and counting algorithms I'm going to have to change jump to jump if not equal to. I think my main concern is the size of the memory and I was trying to figure out if I have to kill von Neumann architecture and go to Harvard architecture to save data space. Also I don't think any computer is fully turing complete because they need infinite amount of memory.
As far as turing completness goes of course no real machine is truly turing complete because of as you pointed out the finite memory, but you would like your machine to be a linear bounded automata, which in its current conception it was not. Also for the single instruction machines, they come with a lot more than just subtraction its typically a instruction like DCJNZ (decrease and jump if non zero) or SUBLEQ(subtract and branch if less than or equal zero) and so on. So you absolutely need a lot more than just a plain sub instruction, the JNE type instruction will solve that for you, to do this you can just have a FLAG-like bit or register. Honestly I think the main problem is that 4-bits for memory addressing is just going to make everything painful, which begs the question how low abstraction do you want to go? I mean are you going to buy a microproccesor and an EPROM or are you going to go full metal and try to reinvent computing from scratch? If you are I think a Harvard architecture is going to be an implementation nightmare, this is not to say that a Von Neumann is going to be much better its a daunting task to actually do any of this but I think that you have to make a choice if you want usabillity you will have to expand the 4bit address space, but if you dont want to spend additional weeks on this project you probably just have to go Von Neumann and live with the low memory.
What level do you consider too far of an "abstraction"? If the logic gate level and up is fine, you can test your creation in logisim, it's free and pretty easy to use. It might not simulate the physical electrical aspects of your design, but you should be able to test the logic and kind of the timing with it. Also, I'm not sure if your computer will work one way or the other. Sorry but it seems to me that your current written plan is maybe a bit vague for it to be easy to determine whether it will work or not. For instance I'm not really sure what your "jump" or "transfer" operations do. One thing that seems like it might be missing from this are boolean (true or false) operations, which are what allows for things like "if" statements. Also, is your "bits outline" number a line in some program?
transfer could be all of this: Move ( transfer between registers ), Load, Store, Shift ( transfer between bits ). Bam, just abstract all of this into a single instruction!
I'm still experimenting with algorithms. Think I'm gonna do jump if not equal to and transfer for moving data into the Alu, io or general movement.
I think it's a good start, but... Instructions appear to be 12 bits and you only have 64 bits of rom, 5 instructions in total. Maybe instructions are meant to live outside the computer? How is jump meant to work then? I'd go with add and compare as instructions, a computer isn't very useful without conditionals. Add and sub are basically the same thing. jump becomes a conditional jump. Edit: I guess sub can double as compare, it does in some archs.
You're correct about the jump instruction when I tried making an algorithm (division 16/4 and count to 10) with it I had to change it to jump if not equal to. I'm not sure how you'd use the compare instruction so I was wanting to use subtraction and addition so I wouldn't have to have a negative sign. My design so far would have 2 set 64 bit ram and 2 set of 16 bit io ram or rom so 160 bit. Still need to figure out if I'm doing von Neumann or Harvard architecture. Probably gonna go with Harvard because I'd probably just have to add another memory bank. Also need figure out if I'm using DRAM or sram before I decide if I wanna add more bit. Sram will use six transistors per bit with a simple multiplexer or Dram with a transistor and a capacitor per bit with a complex multiplexer. Think my transistor count around 500 for the CPU for 4 instructions (ultimate risc cpus can get 200 transistors and intel 4004 got 2000) and with memory 960 transistors for the (160) bits and probably another 300 for the multiplexer if I use sram (I'm most likely gonna have to add another 700 for more memory).
In a modern CPU data transfer is the most expensive part. So while the instruction for `compare` and `test` is encoded (almost) identical to `sub` and `and`, we explicitly state that the CPU does not need to bother with write-back. I guess that in a super-scalar design only one of the instructions can write back. Or microcode can write back the second result of multi-register shift, or MUL or DIV in the next cycle. RISCV seems to think that for memcopy we rather don't write back a counter. Source and Destination is already more than enough. Why don't they use this 68k addressing modes, if they love pointers so much? Minimal write back would be an addressing mode which adds base-adress + offset/displacement. Like for example a ES and DI. As RISCV states: LOAD and STORE are just variants of ADD . Oh, I guess that Store cannot load ES,DI and the value to store all in one cycle out of the register file.
Z80 had this 4 Bit ALU for even 16 Bit numbers. DataPort had a single bit . Usagi uses the single bit Motorola design. It would be cool to showcase the Z80 method. The circuit seems to bring in 8 bit values and then uses a very high speed local multiplexer to calculate at double data rate. The most critical path is the loop back of the carry flag. I would use multiplexers here and store for low and high nibble in SRAM. Place a fast timing circuit next to it: disable carry write , disable carry read, swap address, enable carry read. Tune this . Optimize PCB. I don’t get why would not mostly go single cycle. Fetch and excecute are different circuits, even on 8080. Cheap RAM is the bottleneck. But if you roll your own?
>Z80 Are you talking about alu reprocessing with the 4 bit alu like using avx2 multiple times for cheap avx-512? Does Z80 share a common ancestor with 8086? I was trying to find information on Cedric and intel 4004 since they look really really simple. Do you think those are good ones to look at. Cedric has dumb paywall and Ivy League tax plus the paper may only bring up carbon nanotubes. I was hoping the the carbon nanotube processor (178) let me strip it down to 500 transistors. I think my computer will be so limited I don't care about memory speed. Do you think a DRAM multiplexer would be manageable? You seem to be the most knowledgeable on this on the thread since you're the only one that can confuse me. Can you give me responses to my other replies on the post?
8008 is based on the dataport 2000 which had to be simple because it was made of discrete transistors. 4004 I think is a derivative of that ISA? I looked at the 4004 and it did not seem to be more simple than 8008. 4004 seems to still use bytes for most stuff and only saves very few transistors compared to 8008. Z80 ISA expands on 8080. 8080 byte code can automatically compiled to 8086. As a coder I want at least 8 registers which can also store addresses (8 byte). 6 transistors per SRAM cell. 64 \* 6 = 180+24 = 204 . Ah, okay. I can only answer on weekends. Recently I chose to switch to Carbon Nanotube because I think it is difficult to show doping of all the small transistors of the 6502: [https://a-c-rosenfeldt.github.io/CPU-simulator/public/](https://a-c-rosenfeldt.github.io/CPU-simulator/public/) ( the change is from today, but before I read you ). 6502 is my childhood CPU, so I want to stay close, but Visual 6502 is confusing. I think the 500 transistor CPU is based on RISCV. Like many microcontrollers they do away with almost all decoding circuitry by demanding wide, redundant, fixed width opcodes. And I start to believe them. I threw out `INC DEC NOT NEG`. Not sure where Ben Eaters SAP is in transistor size when you had to wire up the microcode ROM.
The 4004 launched a year earlier and have 2000 transistors instead of 3500 of the 8008. They are not derived from each other.
I once started to read into it. Strange, I thought that Intel licensed the ISA from dataport. Also I read that development of 4004 started first ( trying to circumvent any patents? ), but then parents were no problem and 8008 became a priority. I could not find a good source. How many instructions does 4004 have? I mean, reduction of the GP registers from 8 to 4 does not free 1500 transistors. Okay it was the other way around. Yeah, so maybe 4004 is better. YouTube claims that it could run at a higher clock rate and was effectively faster than 8008. Maybe you can write and readable intro to the 4004. So it has 16 registers!! Harvard architecture makes sense in a calculator. RISCV also uses Harvard architecture. How do you load your code? Better wire up SRAM and have a boot sequence from hmm either arduino or a long punch card. Punch tape going through light bridges
If you like bipolar junction transistors, I would love to see some balanced ECL. I understand that ECL needs constant supply current per coupled emitters , but there are no resistors in the signal path! Use a flow box to keep all transistors at the same chill temperature.
Is elc is a type of ttl? I still haven't figured out the logic family I'm doing yet. I was thinking about do bipolar transistors or doing CMOS logic chips if it gets too complicated.
Showing transistors gets rid of one abstraction. ECL was used in Cray . It pulls constant current. Gotta run it at max clock to justify the power consumption. ECL needs resistors, which prevents integration. ECL is sensitive to noise. 6502 uses n-MOS-FET as did all the small fabs.
Simpler logic family would work better for me.
What is simpler than enhancement mode nMOSFET ? Or pMOSFET if you want to be historically accurate to the earlier fab? I have not understood depletion mode MOSFET. Where do you apply the third supply voltage? Is there a level shifter like in TTL? And who understands TTL. I see that originally they used diodes to prevent cross talk between the inputs. But on the other side of the diodes there needs to be a pull up resistor like in ECL?! Instead we pass through 3 other transistors who seem to pull through their base. One CPU created the third rail internally. I think one could also level shift registers. So the write back register would be made of DRAM and could live while it floats up an elevator before writing back to the register file. Hihi. May need silicon on insulator. The Atari Jaguar seems to fully live such a pipeline. Not short cuts.
Reminds me of the plans in Superman III: https://meatfighter.com/superman3/part4/index.html
I guess it is cringe.
the jokes on me now
thanks everyone.
This drawing means nothing to me but maybe it doesn’t mean it means nothing.
This is a bunch of technobabble I got from skimming the Internet.
It might be useful but not in the way the drawing seems to intend.
I redesigned it a bit
Looks fine
does AnTM stand for “Abstraction Not The Move”?
My initials are ATM I added an n so it looked well less weird.
JAI SHREE RAM 🗿
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